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3a bus termination regulator copyright ? anpec electronics corp. rev. a.8 - oct., 2003 apl5331 www.anpec.com.tw 1 anpec reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. ? ? ? ? ? provide bi-direction current - sourcing or sinking current up to 3a ? ? ? ? ? 1.25v/0.9v output for ddr i/ii applications ? ? ? ? ? fast transient response ? ? ? ? ? high output accuracy - 20mv over load, vout offset and temperature ? ? ? ? ? adjustable output voltage by external resistors ? ? ? ? ? current-limit protection ? ? ? ? ? on-chip thermal shutdown ? ? ? ? ? shutdown for standby or suspend mode ? ? ? ? ? simple sop-8, sop-8-p with thermal pad, to-252- 5 and to-263-5 packages features general description (cont.) on-chip thermal shutdown provides protection against any combination of overload that would create ex- cessive junction temperature. the output voltage of apl5331 track the voltage at vref pin. a resistor divider connected to vin, gnd and vref pins is used to provide a half voltage of vin to vref pin. in addition, an external ceramic capacitor and an open- drain transistor connected to vref pin provides soft- start and shutdown control respectively. pulling and holding the vref to gnd shuts off the output. the output of apl5331 will be high impedance after be- ing shut down by vref or thermal shutdown function. applications ? ddr i/ii sdram termination ? sstl-2/3 termination voltage ? applications requiring the regulator with bi-direction 3a current capability pin configuration to-252-5 (top view) vout vref vcntl gnd vin 12345 tab is vcntl to-263-5 (top view) vin gnd vcntl vref vout 1 2 3 4 5 tab is vcntl sop-8 (top view) 1 2 3 45 6 7 8 vin gnd vref vout vcntl vcntl vcntl vcntl general description the apl5331 linear regulator is designed to provide a regulated voltage with bi-directional output current for ddr-sdram termination. the apl5331 integrates two power transistors to source or sink current up to 3a. it also incorporate current-limit, thermal shut- down and shutdown control functions into a single chip. current-limit circuit limits the short-circuit current. 1 2 3 45 6 7 8 vin gnd vref vout nc vcntl nc nc sop-8-p (top view) = thermal pad nc = no internal connection (connected to gnd plane for better heat dissipation)
copyright ? anpec electronics corp. rev. a.8 - oct., 2003 apl5331 www.anpec.com.tw 2 package code k : sop-8 ka : sop-8-p u5 : to-252-5 g5 : to-263-5 tem p. range c : 0 to 70 o c handling code tr : tape & reel lead free code l : lead free device blank : orginal device apl5331 handling code tem p. range package code apl5331 xxxxx apl5331kc-tr : apl5331kac-tr : xxxxx - date code apl5331 xxxxx apl5331u5c-tr : apl5331g5c-tr : xxxxx - date code lead free code ordering and marking information pin description pin name i/o description vin i main power input pin. connect this pin to a voltage source and an input capacitor. the apl5331 sources current to vout pin by controlling the upper npn pass transistor, providing a current path from vin pin. gnd o power and signal ground. connect this pin to system ground plane with shortest traces. the apl5331 sinks current from vout pin by controlling the lower npn pass transistor, providing a current path to gnd pin. this pin is also the ground path for internal control circuitry. vcntl i power input pin for internal control circuitry. connect this pin to a voltage source, providing a bias for the internal control circuitry. a bypass capacitor is usually connected near this pin. vref i reference voltage input and active-low shutdown control pin. apply a voltage to this pin as a reference voltage for the apl5331. connect this pin to a resistor divider, between vin and gnd, and a capacitor for soft-start and filtering noise purposes. applying and holding this pin low by an open-drain transistor to shut down the output. vout o output pin of the regulator. connect this pin to load. output capacitors connected this pin improves stability and transient response. the output voltage tracks the reference voltage and is capable of sourcing or sinking current up to 3a. block diagram gnd vout vin vcntl vref current lim it therm al lim it voltage regulation shutdown
copyright ? anpec electronics corp. rev. a.8 - oct., 2003 apl5331 www.anpec.com.tw 3 symbol parameter range unit v cntl vcntl supply voltage 3.1 ~ 6v v v in vin supply voltage 1.6 ~ 3.5 v v ref vref input voltage 0.8 ~ 1.75 v i out vout output current (note1, 2) -3 ~ +3 a t j junction temperature 0 ~ 125 o c symbol parameter rating unit v cntl vcntl supply voltage, vcntl to gnd -0.2 ~ 7 v v in vin supply voltage, vin to gnd -0.2 ~ 3.9 v p d power dissipation internally limited w t j junction temperature 150 o c t stg storage temperature -65 ~ 150 o c t sdr soldering temperature, 10 seconds 300 o c v esd minimum esd rating (human body mode) 3 kv note1 : the symbol ?+? means the vout sources current to load; the symbol ?-? means the vout sinks current to gnd. note2 : the max. i out varies with the t j . please refer to the typical characteristics. absolute maximum ratings thermal characteristics symbol parameter rating unit ja thermal resistance in free air sop-8 sop-8-p to-252-5 to-263-5 160 80 80 50 c/w recommended operating conditions
copyright ? anpec electronics corp. rev. a.8 - oct., 2003 apl5331 www.anpec.com.tw 4 electrical characteristics refer to the typical application circuit. these specifications apply over, v cntl =3.3v, v in =2.5v/1.8v, v ref =0.5v in and t j = 0 to 125c, unless otherwise specified. typical values refer to t j =25c. apl5331 symbol parameter test conditions min typ max unit output voltage v out vout output voltage i out =0a v ref v system accuracy over temperature, vout offset, and load regulation -20 20 mv i out =+10ma -14 -9 v os vout offset voltage (v out ?v ref ) i out =-10ma 2 8 mv i out =+10ma to +3a -6 -3 load regulation i out = -10ma to -3a 7 12 mv protection sourcing current t j =25c (v in =2.5v) t j =125c +3.3 +3.6 +3.1 sinking current t j =25c (v in =2.5v) t j =125c -3.3 -3.6 -3.1 sourcing current t j =25c (v in =1.8v) t j =125c +2.9 +3.2 +2.6 i lim current limit sinking current t j =25c (v in =1.8v) t j =125c -2.9 -3.2 -2.6 a t sd thermal shutdown temperature rising t j 150 o c thermal shutdown hysteresis 40 o c input current i out =0a 2 4.5 6 i out = 3a (normal operation), v cntl =5v 50 110 i cntl vcntl supply current v ref =gnd (shutdown) 2.6 ma v ref =1.25v/0.9v (normal operation) 150 500 na i vref vref bias current (the current flows out of vref) v ref =gnd (shutdown) 20 40 a shutdown control shutdown threshold voltage 0.2 0.35 0.65 v
copyright ? anpec electronics corp. rev. a.8 - oct., 2003 apl5331 www.anpec.com.tw 5 typical application circuit c out : 470 f, esr=25m ? r 1 , r2 : 1k ? , 1% q1 : apm2300 ac v cntl +3.3v c cntl 47uf v out +1.25v/0.9v -3~+3a c ss 0.1uf gnd r 1 1k r 2 1k v in +2.5v/1.8v gnd c in 470uf q 1 shutdown c out 470uf v ref gnd vref vin vout vcntl note : since r 1 and r 2 are very small, the voltage offset caused by the bias current of vref can be ignore. 2. v out =1.4v application v cnt l +5v c cnt l 47 f v out +1.4v/ -3~+3a c ss 0.1 f gnd r 1 1k r 2 1k v in +2.8v gnd c in 470 f c out 470 f v ref gnd vr ef vin vou t vcntl 1. v out =1.25v/0.9v application
copyright ? anpec electronics corp. rev. a.8 - oct., 2003 apl5331 www.anpec.com.tw 6 2.0 2.5 3.0 3.5 4.0 4.5 5.0 - 50 - 25 0 25 50 75 100 125 -5.0 -4.5 -4.0 -3.5 -3.0 -2.5 -2.0 - 50 - 25 0 25 50 75 100 125 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 -50 -25 0 25 50 75 100 125 typical characteristics sourcing current-limit vs junction temperature current-limit, ilim (a) junction temperature (c) vref bias current vs junction temperature junction temperature (c) vref bias current, i vref ( a) junction temperature (c) vref shutdown threshold (v) junction temperature (c) current-limit, ilim (a) sinking current-limit vs junction temperature vref shutdown threshold vs junction temperature v ref =1.25v/0.9v 0.1 0.2 0.3 0.4 0.5 0.6 -50 -25 0 25 50 75 100 125 v cntl =5v v cntl =3.3v v cntl =5v,v in =2.5v v cntl =3.3v,v in =2.5v v cntl =5v,v in =1.8v v cntl =3.3v,v in =1.8v v cntl =5v,v in =1.8v v cntl =3.3v,v in =1.8v v cntl =3.3v,v in =2.5v v cntl =5v,v in =2.5v
copyright ? anpec electronics corp. rev. a.8 - oct., 2003 apl5331 www.anpec.com.tw 7 0 2 4 6 8 10 12 14 16 18 20 22 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 -50-250 255075100125 -16 -14 -12 -10 -8 -6 -4 -2 0 2 4 6 -50 -25 0 25 50 75 100 125 typical characteristics (cont.) vout offset voltage vs junction temperature vout offset voltage, v os (mv) junction temperature (c) v ref =1.25v/0.9v quiescent vcntl current vs junction temperature junction temperature ( c) vref bias current vs vref supply voltage vref supply votage, v ref (v) vref bias current, i vref ( a) i out =-10ma i out =+10ma quiescent vcntl current (ma) i out =0a v cntl =5v v cntl =3.3v t j =25c
copyright ? anpec electronics corp. rev. a.8 - oct., 2003 apl5331 www.anpec.com.tw 8 operating waveforms 1. load transient response : i out = +10ma -> +3a -> +10ma - v in = 2.5v, v cntl = 3.3v - v ref is 1.250v supplied by a regulator - c out = 470 f/10v, esr = 30m ? - i out slew rate = 3a/ s i out = +10ma -> +3a v out i out ch1 : v out , 20mv/div, dc, offset = 1.250v ax1 : i out , 1a/div time : 1 s/div ch1 : v out , 20mv/div, dc, offset = 1.250v ax1 : i out , 1a/div time : 20 s/div ch1 : v out , 20mv/div, dc, offset = 1.250v ax1 : i out , 1a/div time : 1 s/div i out = +10ma -> +3a -> +10ma i out = +3a -> +10ma v out i out +3a +10ma v out i out 2. load transient response : i out = -10ma -> -3a -> -10ma - v in = 2.5v, v cntl = 3.3v - v ref is 1.250v supplied by a regulator - c out = 470 f/10v, esr = 30m ? - i out slew rate = 3a/ s i out = -10ma -> -3a v out i out ch1 : v out , 20mv/div, dc, offset = 1.250v ax1 : i out , 1a/div time : 1 s/div ch1 : v out , 20mv/div, dc, offset = 1.250v ax1 : i out , 1a/div time : 20 s/div ch1 : v out , 20mv/div, dc, offset = 1.250v ax1 : i out , 1a/div time : 1 s/div i out = -10ma -> -3a -> -10ma i out = -3a -> -10ma v out i out -3a -10ma v out i out load regulation = -2.8mv load regulation = +6.2mv
copyright ? anpec electronics corp. rev. a.8 - oct., 2003 apl5331 www.anpec.com.tw 9 operating waveforms (cont.) 3. load transient response : i out = +3a -> -3a -> +3a - v in = 2.5v, v cntl = 3.3v - v ref is 1.250v supplied by a regulator - c out = 470 f/10v, esr = 30m ? - i out slew rate = 3a/ s i out = +3a -> -3a ch1 : v out , 50mv/div, dc, offset = 1.250v ax1 : i out , 2a/div time : 1 s/div ch1 : v out , 50mv/div, dc, offset = 1.250v ax1 : i out , 2a/div time : 20 s/div ch1 : v out , 50mv/div, dc, offset = 1.250v ax1 : i out , 2a/div time : 1 s/div i out = +3a -> -3a -> +3a i out = -3a -> +3a 4. short-circuit test - v in = 2.5v, v cntl = 3.3v v out is shorted to gnd v out i out ch1 : v out , 500mv/div, dc, ax1 : i out , 2a/div time : 5ms/div ch1 : v out , 500mv/div, dc, ax1 : i out , 2a/div time : 5ms/div v out is shorted to v in (2.5v) v out i out v out i out v out i out +3a -3a v out i out v out i out
copyright ? anpec electronics corp. rev. a.8 - oct., 2003 apl5331 www.anpec.com.tw 10 application information general the apl5331 is a linear regulator and is capable of sourcing or sinking current up to 3a. the apl5331 has fast transient response, accurate output voltage (small voltage offset, load regulation), active-low shut- down control and fault protections (current-limit, ther- mal shutdown). the apl5331 is available in several packages to meet different of power dissipation in requirement various applications. output voltage regulation the output voltage at vout pin tracks the reference voltage applied at vref pin. two internal npn pass transistors controlled by separate high bandwidth er- ror amplifiers regulate the output voltage by sourcing current from vin pin or sinking current to gnd pin. the base currents of the pass transistors are pro- vided by vcntl pin. an internal kelvin sensing scheme use at the vout pin for perfect load regula- tion at various load current. to prevent the two pass transistors from shoot-through, a small voltage offset is created between the positive inputs of the two error amplifiers. this results in higher output voltage while the regulator sinks light or heavy load current. since the apl5331 exhibits very fast load transient response, lesser amount of capacitors can be use. in addition, capacitors with high esr can also be use. shutdown and soft-start the vref pin is a dual-function input pin, acting as reference input and shutdown control input. apply- ing and holding a voltage below 0.35v(typ.) to vref pin shuts down the output of the regulator. an npn transistor or n-channel mosfet is used to pull down the vref while applying a ?high? signal to turn on the transistor. when shutdown function is active, the two pass transistors are turned off and the imped- ance of the vout is about 10m ? (typ.), sourcing or sinking no current. when release the vref pin, the current through the resistor divider charges the soft- start capacitor to initiate a soft-start cycle. the output voltage tracks the rising vref. the soft start process limits the input surge current. thermal shutdown an thermal shutdown circuit limits the junction tem- perature of the apl5331. when the junction tem- perature exceeds t j = +150 o c, a thermal sensor turns off both pass transistors, allowing the device to cool down. the regulator starts to regulate again after the junction temperature reduces by 40 o c, resulting in a pulsed output during continuous thermal overload conditions. the thermal limit designed with a 40 o c hysteresis lowers the average t j during continuous thermal overload conditions, extend life time of apl5331. current limit the apl5331 monitors sourcing and sinking current, and limits the maximum output current to prevent dam- ages during overload or short-circuit, to increase the input voltage of vin or vcntl will get higher current-limit points.
copyright ? anpec electronics corp. rev. a.8 - oct., 2003 apl5331 www.anpec.com.tw 11 application information power inputs input power sequence are not required for vin and vcntl. however, do not apply a voltage to vout when there is not voltage vcntl. this is due to the internal parasitic diodes between vout to vin and vout to vcntl which will be forward bias. the apl5331 can source few current or sinks current up to 3a for load when the input voltage at vin is not present. reference voltage a reference voltage is applied at the vref pin by a resistor divider between vin and gnd pins. normally the bias current of the vref pin flows out of the ic and is about 150na(typ.), creating voltage offset at the resistor divider and affecting the output voltage accuracy. the recommended resistor is <5k ? to maintain the accuracy of the output voltage. an ex- ternal bypass capacitor is also connected to vref. the capacitor and the resistor divider form a low- pass filter to reduce the inherent reference noise from vin. a ceramic capacitor can be use and is selected to be greater than 0.1 f. connected the capacitor as close to vref as possible for optimal effect. more capacitance and large resistor divider will increase the soft-start interval. do not place any additional load- ing on this reference input pin. output capacitor the apl5331 requires a proper output capacitor to maintain stability over full temperature and current ranges, and improve transient response. the output capacitor selection is dependent upon the esr (equivalent series resistance) and capacitance of the output capacitor over full temperature range. the fol- lowing chart shows the stable region of the output capacitor for apl5331. the stable region is above the curve, indicating minimum required esr and capacitance to maintain stability. however, the out put capacitor should have an esr less than 1 ? . ultra-low-esr capacitors, such as ceramic chip capacitors, may promote under-damped transient response, but proper ceramic chip capacitors placed near loads can be used as decoupling capacitors. a low-esr solid tantalum and aluminum electrolytic ca- pacitor (esr<1 ? ) works extremely well and provides good transient response and stability over temperature. the output capacitors are also used to reduce the slew rate of load current and help the apl5331 to minimize variations of the output voltage, improving transient response. for this purpose, the low-esr capacitors are recommended and depend on the step- ping and slew rate of load current. input capacitor the input capacitors of vcntl and vin pins are not required for stability but for supplying surge currents during large load transients, this will prevent the in- put rail from drooping and improve the performance of the apl5331. because of parasitic inductors from voltage sources or other bulk capacitors to the vcntl and vin pins will limit the slew rate of the surge cur- rents during large load transients, resulting in voltage drop at vin and vcntl pins. 0 5 10 15 20 25 10 100 1000 capacitance( f) esr (m ? ) stable region 0 5 10 15 20 25 10 100 1000 capacitance( f) esr (m ? ) stable region
copyright ? anpec electronics corp. rev. a.8 - oct., 2003 apl5331 www.anpec.com.tw 12 a capacitor of 1 f (ceramic chip capacitor) or greater (aluminum electrolytic capacitor) is recommended to connect near vcntl pin. for vin pin, an aluminum electrolytic capacitor (>50 f) is recommended. it is not necessary to use low-esr capacitors. layout and thermal consideration the input capacitors for vin and vcntl pins are normally placed near each pin for good performances. ceramic decoupling capacitors at output must be placed as close to the load to reduce the parasitic inductors of traces. it is also recom- mended that the apl5331 and output capacitors are placed near the load for good load regulation and load transient response. the negative pins of the in- put and output capacitors and the gnd pin of the apl5331 should connect to analog ground plane of the load. see figure 1. the sop-8-p utilizes a bottom thermal pad to minimize the thermal resistance of the package, making the package suitable for high current applications. the thermal pad is soldered to the top ground pad and is connected to the internal or bot- tom ground plane by several vias. the printed circuit board (pcb) forms a heat sink and dissipates most of the heat into ambient air. the vias are recom- mended to have proper size to retain solder, helping heat conduction. thermal resistance consists of two main elements, jc (junction-to-case thermal resistance) and ca (case-to-ambient thermal resistance). jc is speci- fied from the ic junction to the bottom of the thermal pad directly below the die. ca is the resistance from the bottom of thermal pad to the ambient air and it includes cs (case-to-sink thermal resistance) and sa (sink-to-ambient thermal resistance). the speci- fied path for heat flow is the lowest resistance path and it dissipates majority of the heat to the ambient air. typically, ca is the dominant thermal resistance. therefore, enlarging the internal or bottom ground plane reduces the resistance ca . the relationship between power dissipation and temperatures is the following equation : p d = (t j - t a ) / ja where, p d : power dissipation t j : junction temperature t a : ambient temperature ja : junction-to-ambient thermal resis- tance thermal pad die top ground pad printed circuit board internal ground plane vias ambient air 118 mil 102 mil sop-8-p figure 2 shows a board layout using the sop-8-p package. the demo board is made of fr-4 material and is a two-layer pcb. the size and thickness are 65mm* 65mm and 1.6mm. an area of 140mil*105mil on the top layer is use as a thermal pad for the apl5331 and this is connected to the bottom layer by vias. the bottom layer using 2 oz. copper acts as the ground plane for the system. the pcb and all components on the board form a heat sink. the ja of the apl5331(sop-8-p) mounted on this demo board is about 37 o c/w in free air. assuming the t a =25 o c and the maximum t j =150 o c (typical thermal limit temperature), the maximum power dissipation is calculated as : figure 1 package top and side view
copyright ? anpec electronics corp. rev. a.8 - oct., 2003 apl5331 www.anpec.com.tw 13 p d (max) = (150 - 25) / 37 = 3.38w if the t j is designed to be below 125 o c, the calcu- lated power dissipation should be less than : p d = (125 - 25) / 37 = 2.70w figure 2(a) topover layer figure 2(b) top layer figure 2(c) bottom layer apl5331 apl5 33 1
copyright ? anpec electronics corp. rev. a.8 - oct., 2003 apl5331 www.anpec.com.tw 14 packaging information millimeters inches dim min. max. min. max. a 1.35 1.75 0.053 0.069 a1 0.10 0.25 0.004 0.010 d 4.80 5.00 0.189 0.197 e 3.80 4.00 0.150 0.157 h 5.80 6.20 0.228 0.244 l 0.40 1.27 0.016 0.050 e1 0.33 0.51 0.013 0.020 e2 1.27bsc 0.50bsc 18 8 h e e1 e2 0.015x45 d a a1 0.004max. 1 l sop-8 pin ( reference jedec registration ms-012)
copyright ? anpec electronics corp. rev. a.8 - oct., 2003 apl5331 www.anpec.com.tw 15 packaging information millimeters inches dim min. max. min. max. a 1.35 1.75 0.053 0.069 a1 0.10 0.25 0.004 0.010 d 4.80 5.00 0.189 0.197 d1 3.00ref 0.118ref e 3.80 4.00 0.150 0.157 e1 2.60ref 0.102ref h 5.80 6.20 0.228 0.244 l 0.40 1.27 0.016 0.050 e1 0.33 0.51 0.013 0.020 e2 1.27bsc 0.50bsc 18 8 sop-8-p pin ( reference jedec registration ms-012) h e e1 e2 0.015x45 d a a1 0.004max. 1 l e1 d1
copyright ? anpec electronics corp. rev. a.8 - oct., 2003 apl5331 www.anpec.com.tw 16 packaging information to-252-5 m illim eters inches dim min. max. min. max. a 6.40 6.80 0.25 0.26 b 5.20 5.50 0.20 0.21 c 6.80 7.20 0.26 0.27 d 2.20 2.80 0.08 0.11 d1 5.2ref 0.205ref e1 5.3ref 0.209ref p 1.27ref 0.05ref s 0.50 0.80 0.02 0.03 h 2.20 2.40 0.08 0.09 j 0.45 0.55 0.01 0.02 k 0.45 0.60 0.018 0.024 l 0.90 1.50 0.03 0.06 m 5.40 5.80 0.21 0.22 a b m c d j h l p s k e1 d1
copyright ? anpec electronics corp. rev. a.8 - oct., 2003 apl5331 www.anpec.com.tw 17 packaging information to-263-5 millimeters inches dim min. max. min. max. a 4.06 4.83 0.160 0.190 b 0.50 0.99 0.020 0.039 b1 1.52 1.83 0.060 0.072 c 0.457 0.736 0.018 0.029 c1 1.14 1.40 0.045 0.055 d 8.25 9.66 0.325 0.380 e 9.65 10.29 0.380 0.405 l 14.60 15.88 0.575 0.625 l1 2.28 2.80 0.090 0.110 l2 1.40 0.055 d a c l2 a1 c1 v e e1 b l l1 b e
copyright ? anpec electronics corp. rev. a.8 - oct., 2003 apl5331 www.anpec.com.tw 18 physical specifications reference jedec standard j-std-020a april 1999 reflow condition (ir/convection or vpr reflow) pre-heat temperature 183 c peak temperature time temperature classification reflow profiles convection or ir/ convection vpr average ramp-up rate(183 c to peak) 3 c/second max. 10 c /second max. preheat temperature 125 25 c) 120 seconds max temperature maintained above 183 c 60 ? 150 seconds time within 5 c of actual peak temperature 10 ?20 seconds 60 seconds peak temperature range 220 +5/-0 c or 235 +5/-0 c 215-219 c or 235 +5/-0 c ramp-down rate 6 c /second max. 10 c /second max. time 25 c to peak temperature 6 minutes max. package reflow conditions pkg. thickness 2.5mm and all bgas pkg. thickness < 2.5mm and pkg. volume 350 mm3 pkg. thickness < 2.5mm and pkg. volume < 350mm3 convection 220 +5/-0 c convection 235 +5/-0 c vpr 215-219 c vpr 235 +5/-0 c ir/convection 220 +5/-0 c ir/convection 235 +5/-0 c terminal material solder-plated copper (solder material : 90/10 or 63/37 snpb) lead solderability meets eia specification rsi86-91, ansi/j-std-002 category 3.
copyright ? anpec electronics corp. rev. a.8 - oct., 2003 apl5331 www.anpec.com.tw 19 r eliability test program test item method description solderability mil-std-883d-2003 245 c , 5 sec holt mil-std-883d-1005.7 1000 hrs bias @ 125 c pct jesd-22-b, a102 168 hrs, 100 % rh , 121 c tst mil-std-883d-1011.9 -65 c ~ 150 c, 200 cycles esd mil-std-883d-3015.7 vhbm > 2kv, vmm > 200v latch-u p jesd 78 10m s , i tr > 100ma carrier tape a j b t2 t1 c t ao e w po p ko bo d1 d f p1
copyright ? anpec electronics corp. rev. a.8 - oct., 2003 apl5331 www.anpec.com.tw 20 application carrier width cover tape width devices per reel sop- 8 / sop-8-p 12 9.3 2500 to- 252 16 13.3 2500 to- 263 24 21.3 1000 a pp lication a b c j t1 t2 w p e 330 1 62 +1.5 12.75+ 0.15 2 0.5 12.4 0.2 2 0.2 12 0. 3 8 0.1 1.75 0.1 f d d1 po p1 ao bo ko t sop- 8 sop-8-p 5.5 1 1.55 +0.1 1.55+ 0.25 4.0 0.1 2.0 0.1 6.4 0.1 5.2 0. 1 2.1 0.1 0.3 0.013 a pp lication a b c j t1 t2 w p e 330 3100 213 0. 5 2 0.5 16.4 + 0.3 -0.2 2.5 0.5 16+ 0.3 - 0.1 8 0.1 1.75 0.1 f d d1 po p1 ao bo ko t to-252 7.5 0.1 1.5 +0.1 1.5 0.25 4.0 0.1 2.0 0.1 6.8 0.1 10.4 0.1 2.5 0.1 0.3 0.05 a pp lication a b c j t1 t2 w p e 380 380 213 0. 5 2 0.5 24 42 0.3 24 + 0.3 - 0.1 16 0.1 1.75 0.1 f d d1 po p1 ao bo ko t to-263 11.5 0.1 1.5 +0.1 1.5 0.25 4.0 0.1 2.0 0.1 10.8 0.1 16.1 0.1 5.2 0.1 0.35 0.013 cover tape dimensions anpec electronics corp. head office : 5f, no. 2 li-hsin road, sbip, hsin-chu, taiwan, r.o.c. tel : 886-3-5642000 fax : 886-3-5642050 taipei branch : 7f, no. 137, lane 235, pac chiao rd., hsin tien city, taipei hsien, taiwan, r. o. c. tel : 886-2-89191368 fax : 886-2-89191369 customer service

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